1. Field of the Invention
The present invention relates to a time division multiple control apparatus. More particularly, it relates to an improvement in the transmission function of the multiple signals.
2. Description of the Prior Art
The electrical devices of vehicles, ships, airplanes, etc., have increased to such an extent that the wiring therefor has become quite complicated with the result that repairs have become quite difficult. In order to overcome these difficulties, it has been proposed to simplify the wiring operation by the use of a multiple control system utilizing a multiple communication system.
The multiple communication system includes a frequency division system and a time division system.
FIG. 1 is a block diagram of a typical time division multiple control system. The control apparatus of FIG. 1 is controlled by two types of signals; a reference timing signal for the reference timing of the control apparatus and a time multiple control signal for controlling the electrical devices.
In FIG. 1, the references 1a - 1n designate electrical devices; 2 designates a central processing device; 3 designates a reference timing signal generating circuit; 4 designates a control signal generating circuit for generating the time division control signal; 5a - 5n designate terminal processing devices corresponding to the electrical devices 1a - 1n; 6a - 6n designate address detecting circuits; 7a - 7n designate synchronizing signal division circuits; 8a - 8n designate timing circuits; 9a - 9n designate signal separating circuits 10a - 10n designate driving circuits; 11 designates a reference timing signal transmission line; and 12 designates a control signal transmission line.
FIG. 2 is a time chart for illustrating the operation of the apparatus of FIG. 1. In FIG. 2, a shows the wave-form of the output of the reference timing signal generating circuit 3; b shows the wave-form of the output of the control signal generating circuit 4; c shows the wave-form of the output of the synchronizing signal separating circuits 7a - 7n; d, e and f show the wave-forms of the output of the timing circuits 8a, 8b, 8n; g, h and i show the wave-forms of the signal division circuits 9a, 9b, 9n; j, k and l designate the wave-forms of the outputs of the driving circuits 10a, 10b, 10n.
The operation of the apparatus of FIG. 1 will be illustrated with reference to the time chart of FIG. 2. The central processing device 2 centrally generates signals for controlling the electrical devices 1a - 1n. The reference timing signal generating circuit 3 generates a reference timing signal pulse P having constant frequency as shown in FIG. 2a. The signal pulse P is transmitted to the control signal generating circuit 4 and is simultaneously transmitted to the reference timing signal transmission line 11. The control signal generating circuit 4 is synchronized with the reference timing signal pulse P to generate the control signal. The control signals comprises control signal pulses Qa - Qn corresponding to the electrical devices 1a - 1b. The synchronizing signal S has a broader pulse width than that of the control signal pulses Qa - Qn. The control signal pulses Qa - Qn are sequentially generated after the synchronizing signal S in the order of Qa, Qb . . . Qn. The control signal pulses Qa - Qn drive the corresponding electrical devices 1a - 1n. The control signal pulse is not generated when the corresponding electrical devices 1a - 1n are not driven. Thus, the control signal generating circuit 4 generates the control signals as shown in FIG. 2b and transmits them to the control signal transmission line 12.
The terminal processing devices 5a - 5n receive the control signals in order to control the electrical devices by the command of the central processing device 2. The terminal processing circuits are the same and, accordingly, only the terminal processing circuit 5a will be discussed in detail. The address detecting circuit 6a detects the address period for transmitting the control signal pulse Qa corresponding to the electrical device 1a. The address detecting circuit 6a comprises a synchronizing signal separating circuit 7a and a timing circuit 8a. The synchronizing signal separating circuit 7a counts the reference timing signal pulses P when the synchronizing signal S or the control signal pulses Qa - Qn are generated. When the synchronizing signal S having the broader pulse width is transmitted, the reset signal pulse T of FIG. 2c is generated and is applied to the timing circuit 8a. The timing circuit 8a comprises a counting circuit. The timing circuit 8a is reset by the reset signal pulse T and counts the reference timing signal pulses P to detect the time for transmitting the control signal pulse Qa corresponding to the electrical device 1a and to generate the address signal pulse Ua of FIG. 2d.
The signal separating circuit 9a comprises a logical AND circuit and is connected to the timing circuit 8a and the control signal transmission line 12 whereby the control signal pulse Qa is divided in the period generating the address signal pulse Ua to generate the driving signal pulse Va of FIG. 2g and to transmit it to the driving circuit 10a. The driving signal pulse Va is generated in the period transmitting the control signal pulse Qa, but is not generated in the period transmitting no control signal pulse Qa.
The driving circuit 10a drives the electrical device 1a from the time the driving signal pulse Va is generated to the time the address signal pulse Ua is generated. The control signal pulse Qa is again transmitted when the next address signal pulse Ua is generated. When the driving signal pulse Va is generated, the electrical device 1a is driven. The driving of the electrical device 1a is stopped when the transmission of the control signal pulse Qa is stopped at the time address signal pulse Ua is being generated.
The other terminal processing devices 5b - 5n operate in a similar manner except that the address signal pulses Ub - Un are generated from the timing circuits 8b - 8n during the period the control signal pulses Qb - Qn are generated corresponding to the electrical devices 1b - 1n.
The electrical devices 1a - 1n can be controlled depending upon the time division multiple control signal transmitted from the central processing device 2. However, the time chart of FIG. 2 illustrates an ideal state. In practice, each circuit element has a delay time. However, this time is usually short and accordingly no difficulties arise. However, the propagation delay time of the timing circuits 8a - 8n which are comprised of counting circuits causes difficulties if the counts are increased.
FIG. 3 wherein like references designate identical or corresponding parts is a time chart for illustrating this difficulty. As shown in FIG. 3c, the address signal pulse Ua generated from the timing circuit 10a has a rising delay time t.sub.1 and a falling delay time t.sub.2. Therefore, the period during which the address signal pulse Ua is generated overlaps the address period for the electrical device 1b. The signal pulse separated by the signal separating circuit 9a is generated as shown in FIG. 3d wherein the signal pulse Va is without error. However, the signal pulse Va' is erroneously generated because of the occurrence of control signal pulse Qb. Therefore, the electrical device 1a is not controlled by the control signal pulse Qa. This time error may also appear during signal transmission.